Відео

Very nice bro , also do on uart tx and rx using verilog code

Hi Aviral, Thanks for the great video! I have seen on some other sources that instead of splitting the Analog and Digital return path, one should have one uniform return plane where analog section should be as far as possible from digital section and isolation can be provided using via fencing, proper IC layout and LC filtering. So which method is better?

Great job 👍👍👍

very informative Sir.. JazakAllah ❣

How to calculate conductor height? Anyone can guide me please.

Please share source file code and testbench

Very good dear sir.

Reflection due to impedance mismatch. Can i say plane discontinuing also?

people tell textbooks are standard references to learn . Sir you proved it wrong by your videous.

good.

waiting.

Sir BLOCK DIAGRAM hame BOSS se milega ya khud hame bnana prega.....Please answer me

Nice

Sir how to add black box in schematic and Pcb also?

Aviral you are a genius , a saviour and a great teacher

Your videos are really helpful

Hi sir

Very Informative Sir. JazakAllah ❤

well done!

Drive link is not working

Good.

Keep up the good work!

Great ! I I'm very glad you'll make FPGA development video series.

Sir 1 year ke baad😅

I guess now will become expert in FPGA. Plz don't brake this chain of series. JazakAllah.

When will we be able to watch the complete video course on UA-cam?

when is this course coming on udemy?

Could you indicate a book about FPGA?

I want to learn like you

Great video. Well explained, thanks !!!

super

Great, thank you! You can also use a polygon pour on the solder layer, as in to expose for connection to a grounding bracket.

Is it possible to update this series topic to DDR4 or DDR5?

Hi, link for files download is no longer available, could you please help to check and bring files back?

Thanks for the very useful tutorial, would you please share the project?

meeeen, the "alt+double left click" saved me, I always wanted to know how to do that. Thanks! 🔥

Thank you for video. LOVE YOU <3

I would hope that you can explain why the next and fext has such shape of crosstalk...

I have a doubt how did u relate Cl= (7Er)/Ll I did not understand how you get the last part cl=1/(zo v) and Ll= zo/v

THANKS!

After clicking on integrated library from design part nothing is created (schematic and pcb folder) please help

Nice explanation, Thank you .

I have a question: Can I bend only the Flex PCB? because I'm designing a Flex cable in Altium Designer, and following this step, I assume that only the Flex PCB is not bending, right?

That explained a lot of concepts . ❤

good.

very good it is work

Thank you so much for such informative lectures,. I have a question about how to analyze dual supply op-amps. Like if we are using both +12 and -12v supplies in our circuit.

thank you so much sir, your way to explain anything is very easy and to the point. i just have few questions that in the output voltage as we see a sudden rise for few milliseconds, so it can damage our circuit, so to overcome this what we do, do we use tvs diodes or any better options?

Sir. Please make videos on Hyper Lynx EmC EMI simulatoon Board sim .. DDR simulation Board sim thermal simulation

Thanks Aviral